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| ON Semiconductort Low Power, High Slew Rate, Wide Bandwidth, JFET Input Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC33181/2/4, MC34181/2/4 series of monolithic operational amplifiers. This JFET input series of operational amplifiers operates at 210 A per amplifier and offers 4.0 MHz of gain bandwidth product and 10 V/s slew rate. Precision matching and an innovative trim technique of the single and dual versions provide low input offset voltages. With a JFET input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC33181/2/4, MC34181/2/4 series of devices are specified over the commercial or industrial/vehicular temperature ranges. The complete series of single, dual and quad operational amplifiers are available in the plastic DIP as well as the SOIC surface mount packages. * Low Supply Current: 210 A (Per Amplifier) 8 MC34181,2,4 MC33181,2,4 8 1 1 P SUFFIX PLASTIC PACKAGE CASE 626 D SUFFIX PLASTIC PACKAGE CASE 751 (SO-8) PIN CONNECTIONS Offset Null Inputs VEE 1 2 3 4 + 8 7 6 5 NC VCC Output Offset Null (Single, Top View) Output 1 Inputs 1 VEE 1 2 3 4 + 1 2 + 8 7 6 5 VCC Output 2 Inputs 2 * * * * * * * * * * * Wide Supply Operating Range: 1.5 V to 18 V Wide Bandwidth: 4.0 MHz High Slew Rate: 10 V/s Low Input Offset Voltage: 2.0 mV Large Output Voltage Swing: -14 V to +14 V (with 15 V Supplies) Large Capacitance Drive Capability: 0 pF to 500 pF Low Total Harmonic Distortion: 0.04% Excellent Phase Margin: 67 Excellent Gain Margin: 6.7 dB Output Short Circuit Protection Offered in New TSSOP Package Including the Standard SOIC and DIP Packages ORDERING INFORMATION Op Amp Function Single Device MC34181P MC34181D MC33181P MC33181D Dual MC34182P MC34182D MC33182P MC33182D Quad MC34184P MC34184D MC34184DTB MC33184P MC33184D MC33184DTB Operating Temperature Range TA = 0 to +70C TA = -40 to +85C TA = 0 to +70C TA = -40 to +85C Package Plastic DIP SO-8 Plastic DIP SO-8 Plastic DIP SO-8 Plastic DIP SO-8 Plastic DIP SO-14 TSSOP-14 Plastic DIP SO-14 TSSOP-14 14 1 (Dual, Top View) 14 1 P SUFFIX PLASTIC PACKAGE CASE 646 14 1 D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14) DTB SUFFIX PLASTIC PACKAGE CASE 948G (TSSOP-14) PIN CONNECTIONS Output 1 Inputs 1 VCC Inputs 2 Output 2 1 2 3 4 5 6 7 + + + + 14 13 12 11 10 9 8 Output 4 Inputs 4 VEE Inputs 3 Output 3 1 4 2 3 TA = 0 to +70C TA = -40 to +85C (Quad, Top View) (c) Semiconductor Components Industries, LLC, 2002 1 March, 2002 - Rev. 2 Publication Order Number: MC34181/D MC34181,2,4 MC33181,2,4 MAXIMUM RATINGS Rating Supply Voltage (from VCC to VEE) Input Differential Voltage Range Input Voltage Range Output Short Circuit Duration (Note 2) Operating Junction Temperature Storage Temperature Range Symbol VS VIDR VIR tSC TJ Tstg Value +36 Note 1 Note 1 Indefinite +150 -60 to +150 Unit V V V sec C C NOTES: 1. Either or both input voltages should not exceed the magnitude of V CC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 1). Representative Schematic Diagram (Each Amplifier) VCC Q8 Q9 Pos C1 Q7 D1 R6 Q4 Q3 R2 I3 R3 VEE 1 5 R4 R5 Q5 I4 Q6 D2 C2 R7 VO D3 Internal Bias Network Neg J1 + Q1 Q2 R1 J2 Null Offsets MC3X181 (Single) Only + 1 25 k MC3X181 Input Offset Voltage Null CIrcuit 5 VEE http://onsemi.com 2 MC34181,2,4 MC33181,2,4 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Input Offset Voltage (RS = 50 , VO = 0 V) Single TA = +25C TA = 0 to +70C (MC34181) TA = -40 to +85C (MC33181) Dual TA = +25C TA = 0 to +70C (MC34182) TA = -40 to +85C (MC33182) Quad TA = +25C TA = 0 to +70C (MC34184) TA = -40 to +85C (MC33184) Average Temperature Coefficient of VIO (RS = 50 , VO = 0V) Input Offset Current (VCM = 0 V, VO = 0V) TA = +25C TA = 0 to +70C TA = -40 to +85C Input Bias Current (VCM = 0 V, VO = 0V) TA = +25C TA = 0 to +70C TA = -40 to +85C Input Common Mode Voltage Range Large Signal Voltage Gain (RL = 10 k, VO = 10 V) TA = +25C TA = Tlow to Thigh Output Voltage Swing (VID = 1.0 V, RL = 10 k) TA = +25C Common Mode Rejection (RS = 50 , VCM = VICR, VO = 0 V) Power Supply Rejection (RS = 50 , VCM = 0 V, VO = 0 V) Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source Sink Power Supply Current (No Load, VO = 0 V) Single TA = +25C TA = Tlow to Thigh Dual Symbol VIO Min Typ Max Unit mV -- -- -- -- -- -- -- -- -- VIO/T IIO -- -- -- IIB -- -- -- VICR AVOL 25 15 VO+ VO- CMR PSR ISC 3.0 8.0 ID -- -- -- -- -- -- +13.5 -- 70 70 -- 0.5 -- -- 1.0 -- -- 4.0 -- -- 10 0.001 -- -- 0.003 -- -- 2.0 3.0 3.5 3.0 4.0 4.5 10 11 11.5 -- 0.05 1.0 2.0 nA 0.1 2.0 4.0 V V/mV V/C nA (VEE +4.0 V) to (VCC -2.0 V) 60 -- +14 -14 86 84 8.0 11 -- -- -- -13.5 -- -- -- -- V dB dB mA A 210 -- 420 -- 840 -- 250 250 500 500 1000 1000 TA = +25C TA = Tlow to Thigh Quad TA = +25C TA = Tlow to Thigh http://onsemi.com 3 MC34181,2,4 MC33181,2,4 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 10 k, CL = 100 pF) AV = +1.0 AV = -1.0 Settling Time (AV = -1.0, RL = 10 k, VO = 0 V to +10 V Step) To Within 0.10% To Within 0.01% Gain Bandwidth Product (f = 100 kHz) Power Bandwidth (AV = +1.0, RL = 10 k, VO = 20 Vpp, THD = 5.0%) Phase Margin (-10 V < VO < +10 V) RL = 10 k RL = 10 k, CL = 100 pF Gain Margin (-10 V < VO < +10 V) RL = 10 k RL = 10 k, CL = 100 pF Equivalent Input Noise Voltage RS = 100 , f = 1.0 kHz Equivalent Input Noise Current f = 1.0 kHz Differential Input Capacitance Differential Input Resistance Total Harmonic Distortion AV = 10, RL = 10 k, 2.0 Vpp < VO < 20 Vpp, f = 1.0 kHz Channel Separation (RL = 10 k, -10 V < VO < +10 V, 0 Hz < f < 10 kHz) Open Loop Output Impedance (f = 1.0 MHz) Symbol SR 7.0 -- ts -- -- GBW BWp fm -- -- Am -- -- en in Ci Ri THD -- |Zo| -- -- -- -- -- -- -- 6.7 3.4 38 0.01 3.0 1012 0.04 120 200 -- -- -- -- -- -- -- -- -- nV/ Hz pA/ Hz pF W % dB 67 34 -- -- dB 3.0 -- 1.1 1.5 4.0 120 -- -- -- -- MHz kHz Degrees 10 10 -- -- s Min Typ Max Unit V/s Figure 1. Maximum Power Dissipation versus Temperature for Package Variations P D , MAXIMUM POWER DISSIPATION (mW) V ICR, INPUT COMMON MODE VOLTAGE RANGE (V) 2400 2000 8/14 Pin Plastic TSSOP-14 SO-14 SO-8 0 -1.0 -2.0 3.0 2.0 1.0 Figure 2. Input Common Mode Voltage Range versus Temperature VCC = +3.0 V to +15 V VEE = -3.0 V to -15 V VIO = 5.0 mV VCC (VCM to VCC) 1600 1200 800 400 0 -55 -40 -20 0 20 40 60 80 100 120 140 160 TA, AMBIENT TEMPERATURE (C) 0 -55 VEE -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 http://onsemi.com 4 MC34181,2,4 MC33181,2,4 Figure 3. Input Bias Current versus Temperature 1000 I IB , INPUT BIAS CURRENT (nA) 100 10 1.0 0.1 0.01 -25 0 25 50 75 100 125 I IB , INPUT BIAS CURRENT (nA) VCC = +15 V VEE = -15 V VCM = 0 V 20 VCC = +15 V VEE = -15 V TA = 25C Figure 4. Input Bias Current versus Input Common Mode Voltage 15 10 5 0.001 -55 0 -10 -5.0 0 5.0 10 TA, AMBIENT TEMPERATURE (C) VICR, INPUT COMMON MODE VOLTAGE (V) Figure 5. Output Voltage Swing versus Supply Voltage V sat , OUTPUT SATURATION VOLTAGE (V) 40 VO, OUTPUT VOLTAGE SWING (V) RL Connected to Ground TA = 25C 30 0 -1.0 -2.0 -3.0 Figure 6. Output Saturation Voltage versus Load Current VCC VCC = +15 V VEE = -15 V TA = +25C Source 20 RL = 10 k +3.0 +2.0 +1.0 0 0 Sink VEE 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 10 0 0 2.0 4.0 6.0 8.0 10 12 14 16 VCC, |VEE|, SUPPLY VOLTAGE (V) IL, LOAD CURRENT (mA) Figure 7. Output Saturation Voltage versus Load Resistance to Ground V sat , OUTPUT SATURATION VOLTAGE (V) V sat , OUTPUT SATURATION VOLTAGE (V) 0 -1.0 -2.0 -3.0 3.0 2.0 1.0 0 1.0 k VEE 10 k 100 k 1.0 M RL, LOAD RESISTANCE TO GROUND () VCC VCC = +15 V VEE = -15 V TA = +25C 0 Figure 8. Output Saturation Voltage versus Load Resistance to VCC VCC -1.0 -2.0 -3.0 3.0 2.0 1.0 0 1.0 k VEE 10 k 100 k 1.0 M RL, LOAD RESISTANCE () VCC = +15 V VEE = -15 V TA = +25C http://onsemi.com 5 MC34181,2,4 MC33181,2,4 Figure 9. Output Short Circuit Current versus Temperature I SC , OUTPUT SHORT CIRCUIT CURRENT (mA) 30 VCC = +15 V VEE = -15 V RL 0.1 VID = 1.0 V Figure 10. Output Impedance versus Frequency VCC = +15 V VEE = -15 V VCM = 0 V VO = 0 V IO = 10 A TA = 25C AV = 1000 100 10 1.0 20 Sink 10 Source 0 -55 |Z O |, OUTPUT IMPEDANCE ( ) 50 75 100 125 300 200 100 -25 0 25 0 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M TA, AMBIENT TEMPERATURE (C) Figure 11. Output Voltage Swing versus Frequency THD, TOTAL HARMONIC DISTORTION (%) 30 VO ,OUTPUT VOLTAGE SWING (V p-p ) 24 18 12 6 0 1.0 k VCC = +15 V VEE = -15 V RL = 10 k THD = 1.0% TA = 25C 1.0 0.8 0.6 0.4 Figure 12. Output Distortion versus Frequency VCC = +15 V VEE = -15 V VO = 2.0 Vpp RL = 10 k TA = 25C AV = 1000 100 0.2 0 10 10 1.0 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 10 k 109 k 1.0 M f, FREQUENCY (Hz) Figure 13. Open Loop Voltage Gain versus Temperature A VOL, OPEN LOOP VOLTAGE GAIN (V/mV) A VOL, OPEN LOOP VOLTAGE GAIN (dB) 70 60 50 40 30 20 -55 100 80 60 40 20 0 Figure 14. Open Loop Voltage Gain and Phase versus Frequency , EXCESS PHASE (DEGREES) VCC = +15 V VEE = -15 V VO = 0 V RL = 10 k TA = 25C Gain Phase 0 45 90 VCC = +15 V VEE = -15 V RL = 10 k f 10 Hz TA = 25C -25 0 25 50 75 100 125 135 180 100 M 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M TA, AMBIENT TEMPERATURE (C) f, FREQUENCY (Hz) http://onsemi.com 6 MC34181,2,4 MC33181,2,4 Figure 15. Normalized Gain Bandwidth Product versus Temperature V OS , OUTPUT VOLTAGE OVERSHOOT (%) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125 VCC = +15 V VEE = -15 V RL = 10 k 100 80 60 40 20 0 GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED) Figure 16. Output Voltage Overshoot versus Load Capacitance VCC = +15 V VEE = -15 V RL = 10 k VO = 100 mVpp -10 V < VO < +10 V AV = +1.0 TA = 25C 10 100 CL, LOAD CAPACITANCE (pF) 1.0 k TA, AMBIENT TEMPERATURE (C) Figure 17. Phase Margin versus Load Capacitance 70 , PHASE MARGIN (DEGREES) 60 50 40 30 20 10 0 10 100 CL, LOAD CAPACITANCE (pF) 1.0 k VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V TA = 25C 10 8.0 6.0 4.0 2.0 0 10 Figure 18. Gain Margin versus Load Capacitance VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V TA = 25C m A m, GAIN MARGIN (dB) 100 CL, LOAD CAPACITANCE (pF) 1.0 k Figure 19. Phase Margin versus Temperature 70 m , PHASE MARGIN (DEGREES) 60 50 40 30 20 10 -55 -25 0 CL = 100 pF VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) CL = 10 pF A m, GAIN MARGIN (dB) 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 -55 -25 Figure 20. Gain Margin versus Temperature CL = 10 pF CL = 100 pF VCC = +15 V VEE = -15 V RL = 10 k to -10 V < VO < +10 V 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) http://onsemi.com 7 MC34181,2,4 MC33181,2,4 Figure 21. Normalized Slew Rate versus Temperature CMR, COMMON MODE REJECTION (dB) 1.1 SR, SLEW RATE (NORMALIZED) 1.0 0.9 0.8 0.7 0.6 0.5 -55 VCC = +15 V VEE = -15 V AV = +1.0 RL = 10 k CL = 100 pF Vin = -10 V to +10 V -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) 140 120 100 80 60 40 20 0 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M VCC = +15 V VEE = -15 V VCM = 3.0 V TA = 25C VCM + ADM VCM VO VO Figure 22. Common Mode Rejection versus Frequency CMR = 20 Log X ADM Figure 23. Input Noise Voltage versus Frequency en , INPUT NOISE VOLTAGE ( nV/ Hz ) VCC = +15 V VEE = -15 V VCM = 0 V TA = 25C PSR, POWER SUPPLY REJECTION (dB) 100 80 60 40 20 0 10 110 Figure 24. Power Supply Rejection versus Temperature Positive Supply 100 VCC, VEE = 3.0 V f 10 Hz 90 Negative Supply 80 -55 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k -25 0 25 50 75 100 125 TA < AMBIENT TEMPERATURE (C) Figure 25. Power Supply Rejection versus Frequency 120 100 80 60 40 20 VCC = +15 V VEE = -15 V TA = 25C ADM + VCC VO VEE Figure 26. Normalized Supply Current versus Supply Voltage |IEE |, I CC , SUPPLY CURRENT (NORMALIZED) 1.2 1.1 1.0 0.9 0.8 0.7 TA = 25C 125C -55C VCC = +15 V VEE = -15 V TA = 25C RL = VO = 0V 0 5.0 10 15 20 VCC, |VEE|, SUPPLY VOLTAGE (V) PSR, POWER SUPPLY REJECTION (dB) 140 +PSR = 20Log +PSR (VCC = 1.5 V) -PSR (VEE = 1.5 V) -PSR = 20Log VO/ADM VCC VO/ADM VEE 0 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M http://onsemi.com 8 MC34181,2,4 MC33181,2,4 Figure 27. Channel Separation versus Frequency 140 CHANNEL SEPARATION (dB) 120 100 80 60 40 20 VCC = +15 V VEE = -15 V TA = +25C 100 k 1.0 M 10 M V O , OUTPUT VOLTAGE (5.0 V/DIV) Figure 28. Transient Response VCC = +15 V VEE = -15 V RL = 10 k AV = +1.0 TA = 25C 0 10 k f, FREQUENCY (Hz) t, TIME (2.0 s/DIV) Figure 29. Small Signal Transient Reponse V O , OUTPUT VOLTAGE (20 mV/DIV) VCC = +15 V VEE = -15 V RL = 10 k AV = +1.0 TA = 25C t, TIME (0.5 s/DIV) http://onsemi.com 9 MC34181,2,4 MC33181,2,4 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K 8 5 -B- 1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M TA M H G 0.13 (0.005) B M D SUFFIX PLASTIC PACKAGE CASE 751-05 (SO-8) ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ A 8 D 5 C E H 1 4 0.25 M B M h B C e A SEATING PLANE X 45 _ q 0.10 A1 0.25 B M L CB S A S http://onsemi.com 10 MC34181,2,4 MC33181,2,4 OUTLINE DIMENSIONS - continued P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE L NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 14 8 B 1 7 A F C N H G D SEATING PLANE L J K M D SUFFIX PLASTIC PACKAGE CASE 751A-03 (SO-14) ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 http://onsemi.com 11 MC34181,2,4 MC33181,2,4 ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 MC34181/D |
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